library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;

library work;
 use work.router_pack.all;

-------------------------------------------------------------------------------
entity mutex_net_8 is
-------------------------------------------------------------------------------
port( 
      -- MUTEX input i/f: --
      R       : in  std_logic_vector(mutex8_width_c-1 downto 0);

      -- MUTEX output i/f: --
      G       : out std_logic_vector(mutex8_width_c-1 downto 0)
);           
-------------------------------------------------------------------------------
end mutex_net_8 ;
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
architecture mutex_net_8_arch of mutex_net_8 is
-------------------------------------------------------------------------------
component mutex_net_4
port( 
      -- MUTEX input i/f: --
      R       : in  std_logic_vector(mutex4_width_c-1 downto 0);

      -- MUTEX output i/f: --
      G       : out std_logic_vector(mutex4_width_c-1 downto 0)
);           
end component;

component mutex_net_4_star
port( 
      -- MUTEX input i/f: --
      R       : in  std_logic_vector(mutex4_width_c-1 downto 0);

      -- MUTEX output i/f: --
      G       : out std_logic_vector(mutex4_width_c-1 downto 0)
);           
end component;

--type mutex_ic is integer 0 to 3 of std_logic_vector(1 downto 0); -- pair width
--signal stage_1_outs : mutex_ic;

signal stage_1_outs : std_logic_vector(mutex8_width_c-1 downto 0);
signal stage_2_outs : std_logic_vector(mutex8_width_c-1 downto 0);
signal stage_3_outs : std_logic_vector(mutex8_width_c-1 downto 0);

signal stage_2_ins  : std_logic_vector(mutex8_width_c-1 downto 0);
signal stage_3_ins  : std_logic_vector(mutex8_width_c-1 downto 0);

begin

u_stage1_1: mutex_net_4
port map( 
      R      => R(3 downto 0),
      G      => stage_1_outs(3 downto 0)
);

u_stage1_2: mutex_net_4
port map( 
      R      => R(7 downto 4),
      G      => stage_1_outs(7 downto 4)
);

-- First stage permutation
stage_2_ins <= stage_1_outs(7 downto 6) & stage_1_outs(3 downto 2) &
               stage_1_outs(5 downto 4) & stage_1_outs(1 downto 0);
 

u_stage2_1: mutex_net_4_star
port map( 
      R      => stage_2_ins(3 downto 0),
      G      => stage_2_outs(3 downto 0)
);

u_stage2_2: mutex_net_4_star
port map( 
      R      => stage_2_ins(7 downto 4),
      G      => stage_2_outs(7 downto 4)
);

-- Second stage permutation
stage_3_ins <= stage_2_outs(7 downto 6) & stage_2_outs(1 downto 0) &
               stage_2_outs(3 downto 2) & stage_2_outs(5 downto 4) ;

u_stage3_1: mutex_net_4_star
port map( 
      R      => stage_3_ins(3 downto 0),
      G      => stage_3_outs(3 downto 0)
);

u_stage3_2: mutex_net_4_star
port map( 
      R      => stage_3_ins(7 downto 4),
      G      => stage_3_outs(7 downto 4)
);

-- Output stage permutation:
G <= stage_3_outs(7 downto 6) & stage_3_outs(3 downto 2) &
     stage_3_outs(1 downto 0) & stage_3_outs(5 downto 4) ;


-------------------------------------------------------------------------------
end mutex_net_8_arch;
-------------------------------------------------------------------------------                 

   
-------------------------------------------------------------------------------
configuration  mutex_net_8_cfg  of mutex_net_8 is
-------------------------------------------------------------------------------
   for mutex_net_8_arch
   end for;
-------------------------------------------------------------------------------
end  mutex_net_8_cfg;              
-------------------------------------------------------------------------------
                 
